Post-Silicon Validation Manager

equal1· Cryo-CMOS
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📍 DublinFullTime

About this role

We are seeking an experienced Silicon Validation Manager to join our silicon design team and lead validation activities for our Quantum SoC controller and integrated quantum solutions. This is a hands-on leadership role spanning FPGA-based pre-silicon verification, post-silicon validation and debug, and lab management, including validation at both room temperature and cryogenic temperatures.

In this position, you will play a key role in shaping Equal1’s validation strategy across multiple global sites, while mentoring a multidisciplinary team delivering next-generation quantum hardware.

Main Duties and Responsibilities

  • Lead post-silicon validation and debug of QSoCs, including digital systems with embedded ARM cores, precision analog/mixed-signal blocks, and RF circuits for qubit control and measurement. This extends to device characterisation across samples, at room and at cryo temperatures.

  • Collaborate with design, verification, architecture, firmware, and quantum engineering teams to rapidly isolate, root-cause, and resolve QSoC-level issues.

  • Manage FPGA-based pre-silicon verification, including emulation of digital, analog, and RF paths, firmware test harnesses, and validation software. This includes RFSoC platforms for early system-level testing of complete multi-qubit quantum systems.

  • Coordinate coherent multi-site lab operations and validation workflows, including procurement, calibration, and maintenance of cryogenic, RF, analog, and digital test infrastructure.

  • Ensure sample board readiness and quality through bring-up, rework, revisions, PCB evaluation, packaging considerations, and controlled distribution.

  • Own the automation and scripting frameworks (Python, C, Bash, or similar) to enable repeatable, accelerated, and scalable device debug, data capture, and regression testing.

  • Provide technical leadership and mentorship for engineers and the quantum measurement team, and shape quantum validation strategy, methodologies, and best practices across global sites.

  • Play a significant role in the architecture and design of next-generation QSoC devices, packaging, and quantum collateral.

Experience and Qualifications

Required

  • Strong understanding of semiconductor device physics, including transistor operation, analog/mixed-signal behaviour, noise, parasitics, process variation, and their impact on system-level performance.

  • Hands-on expertise with digital, analog, and RF debug techniques, including oscilloscopes, logic analyzers, VNAs, spectrum analyzers, SMUs, and high-speed digitizers.

  • Experience validating devices at cryogenic temperatures, including qubit control/readout, RF chains, and coherent measurement methodologies (preferred).

  • Strong FPGA-based pre-silicon verification experience, including RFSoC platforms.

  • Familiarity with PCB and packaging tools such as Altium or Cadence Allegro, and understanding of board-level signal integrity, routing, and component placement considerations.

  • Demonstrated ability in automation and scripting for repeatable, accelerated validation and debug workflows (Python, C, Bash, or similar).

  • Proven leadership of engineering teams and multi-site technical programs, excellent mentorship, collaboration, and problem-solving skills.

Desired Experience

  • Experience in quantum hardware or qubit control systems is highly desirable.

Frequently Asked Questions

Is the salary disclosed for the Post-Silicon Validation Manager position at equal1?
The salary for this Post-Silicon Validation Manager role at equal1 is not publicly listed. Click "Apply Now" to learn more about the compensation package on their official careers page.
Where is the Post-Silicon Validation Manager position at equal1 located?
This Post-Silicon Validation Manager role at equal1 is based in Dublin. The position is listed as on-site or hybrid. Check the full job description or apply directly to confirm the work arrangement.
Is the Post-Silicon Validation Manager role at equal1 full-time or part-time?
This is listed as a FullTime position. It is posted as a Post-Silicon Validation Manager role in the Cryo-CMOS department at equal1.
Which team or department does the Post-Silicon Validation Manager at equal1 belong to?
This Post-Silicon Validation Manager position is part of the Cryo-CMOS department at equal1. See the full job description for more information about the team structure and responsibilities.
How do I apply for the Post-Silicon Validation Manager position at equal1?
Click the "Apply Now" button on this page. You will be redirected to equal1's official application portal hosted on ashby where you can submit your application directly.
When was the Post-Silicon Validation Manager job at equal1 posted?
This Post-Silicon Validation Manager position at equal1 was posted on Mar 2, 2026. Apply as soon as possible — early applications are often reviewed first.
Post-Silicon Validation Manager
equal1
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