Senior ASIC Design Verification Engineer

ethernovia· Engineering
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📍 San Jose, CA

About this role

About Ethernovia, Inc.

Ethernovia is developing the future of Ethernet-based networks to realize the full potential of software-defined and autonomous vehicles, robotics and other intelligent machines. Founded in 2018, the company’s breakthrough data transport and acceleration technology is ushering in a new era of connectivity and capabilities in the vehicle and at the edge, including highly reliable autonomy, over-the-air servicing and AI-backed applications. 

Ethernovia's co-founders are serial technology entrepreneurs with multiple prior successful ventures together. We are well-funded and backed by some of the worlds’ leading technology investors, having secured $154M ($90+M Series-B and $64M Series-A) in total funding to date:

Ethernovia has been recognized in EE Times' prestigious list of the Top 100 Startups for 2025.

With talented employees on 4 continents, we have filed 50+ patents to date.

Join Ethernovia’s team to make a lasting impact on the future of packet processor-centric networking solutions to support the real-time sensor, Physical AI, and control data demands of software-defined autonomy across vehicles, robots and intelligent machines. Come share in our success with pre-IPO shares, competitive compensation, and great benefits while growing your knowledge and career with world class talent. We are looking for talented engineers and leaders who have an entrepreneurial spirit and want to drive cutting edge designs from concept to silicon to the future of mobility.

Senior ASIC Design Verification Engineer

Summary:  

  • As a Senior ASIC Verification Engineer, you will be responsible for all aspects of digital SoC verification.
  • You will work the architects, designers, and SW engineers to plan and execute verification and validation of advanced automotive communication semiconductors and systems.
  • You will contribute to a positive, trusting, and cohesive working environment based on integrity and strong work ethics.
  • This position is located in: San Jose, CA

Key Qualifications:

  • BS and/or MS in Electrical Engineering, Computer Science, or related field
  • Minimum 10+ years of ASIC verification experience
  • Strong understanding of ASIC verification fundamentals and industry standard methodologies
  • Experience with Verilog/System Verilog, UVM, Python, TCL, C/C++
  • Experience with the full verification flow, from spec to coverage analysis to gate level sim
  • Debugging failures in simulation to root cause problems
  • Self-motivated and able to work effectively both independently and in a team

Additional Success Factors:
Experience in any of the following areas:

  • Networking (Ethernet MAC, PHY, Switching, TCP/IP, security, PCIe and other industry standard protocols)
  • Video standards, protocols, processing
  • Digital signal processing filters
  • Third party IP (SerDes, controllers, processors, etc.)
  • Modular and Reusable Testbench architecture
  • Design for re-use of pre and post silicon tests and infrastructure
  • Automation of testbench creation, tests, regression, or EDA tools
  • Knowledge of SystemC and/or DPI

Personal Skills:

  • Excellent communication/documentation skills.
  • Attention to details.
  • Collaboration across multidisciplinary and international teams.

What You Can Expect from Ethernovia:

  • Technology depth and breadth expansion that can’t be found in a large company
  • Opportunity to grow your career as the company grows
  • Pre IPO stock options
  • Cutting edge technology
  • World class team
  • Competitive base salary
  • Flexible hours
  • Medical, dental and vision insurance for employees

Salary Range:

  • The actual offered base salary for U.S. locations will vary depending on factors such as work location, individual qualifications, specializations, experience, skills, job-related knowledge, and internal equity. The annual salary range for this position is $200,000 - $300,000. The compensation package will also include incentive compensation in the form of pre-IPO ISO options, in addition to base salary and a full range of medical and other benefits.

 

Frequently Asked Questions

Is the salary disclosed for the Senior ASIC Design Verification Engineer position at ethernovia?
The salary for this Senior ASIC Design Verification Engineer role at ethernovia is not publicly listed. Click "Apply Now" to learn more about the compensation package on their official careers page.
Where is the Senior ASIC Design Verification Engineer position at ethernovia located?
This Senior ASIC Design Verification Engineer role at ethernovia is based in San Jose, CA. The position is listed as on-site or hybrid. Check the full job description or apply directly to confirm the work arrangement.
Which team or department does the Senior ASIC Design Verification Engineer at ethernovia belong to?
This Senior ASIC Design Verification Engineer position is part of the Engineering department at ethernovia. See the full job description for more information about the team structure and responsibilities.
How do I apply for the Senior ASIC Design Verification Engineer position at ethernovia?
Click the "Apply Now" button on this page. You will be redirected to ethernovia's official application portal hosted on greenhouse where you can submit your application directly.
When was the Senior ASIC Design Verification Engineer job at ethernovia posted?
This Senior ASIC Design Verification Engineer position at ethernovia was posted on Oct 4, 2024. Apply as soon as possible — early applications are often reviewed first.
Senior ASIC Design Verification Engineer
ethernovia
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