Senior/ Staff Physical Design Engineer - EMIR CAD

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in EMIR CAD to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As a Physical Design Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.

You will continuously develop the Electro-Migration and IR Drop (EMIR) flow, working closely at the intersection of Physical Design, Analog/Mixed-Signal design, and Package Engineering.

Key Responsibilities

• Take responsibility on IR drop analysis and signal/power electromigration (EM) flow
• Implement and maintain robust EMIR flows and methodologies using industry-standard tools (Ansys RedHawk-SC, Cadence Voltus, or equivalent)
• Collaborate closely with Analog/SerDes designers to integrate current profiles and ensure robust power delivery to sensitive high-speed IP blocks
• Partner with Package Design engineers to perform Chip-Package-System (CPS) co-analysis flow
• Understand root-cause analysis for voltage drop violations and EM risks
• Support silicon bring-up by correlating simulation results with actual silicon measurements and yield data

Basic Qualifications

• Bachelor's or Master's degree in Electrical Engineering or a related technical field
• 5+ years of hands-on experience in EMIR/Power Integrity analysis for high-performance SoCs or high-speed connectivity products
• Strong proficiency in industry-standard EMIR tools flow development (Ansys RedHawk/RedHawk-SC, or Cadence Voltus)
• Deep understanding of EM/IR challenges in advanced FinFET nodes (7nm, 5nm, 3nm)
• Basic understanding of Place & Route flows, power grid synthesis, extraction (RC), and standard cell architecture
• Proven Proficiency in Python in required, Tcl or Perl preferable for flow automation and data parsing
• Deep understanding of the RedHawk tool, including efficient use of MapReduce and other Ansys proprietary capabilities (including potential use of ad-hoc SDC for context and LSO – Logic State Override)
• Strong understanding of required inputs for creating Scenarios and Analysis Views
• Deep understanding of standard cell and IP abstractions (APL, LIB, AVM), including IP waveform construction from PWL (sim2iprof)

Preferred Experience

• Experience performing Chip-Package-System (CPS) thermal and power co-simulation
• Familiarity with thermal analysis tools and their interaction with electrical performance
• Experience working with sign-off criteria and margins for high-volume production chips
• Basic understanding of timing and P&R
• Good understanding of EM, including deterministic EM (DC, peak, RMS)
• Basic understanding of statistical EM and reliability concepts (SEB, Black’s Equation, FIT, MTTF)
• Basic understanding of packaging, top metal layers, MIM capacitor usage, and power distribution