About this role

Basic Qualifications

Requires a Bachelor’s degree in Electrical or Computer Engineering, or a related Science, Engineering, Technology or Mathematics field. Also requires 8+ years of job-related experience, or a Master's degree plus 6 years of job-related experience. Agile experience preferred.  

 

CLEARANCE REQUIREMENTS: Ability to obtain a Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.

Responsibilities for this Position

Knowledge, Skills and Abilities:

 

Duties and Tasks:

 

  • Collaborate with team leaders to explore and clearly identify real problems and solutions.
  • Develop and define the microarchitecture of new IP to optimize performance, I/O, power consumption, area utilization, recurring cost and security functions.
  • Implement and simulate IP blocks in RTL using SystemVerilog, VHDL, and other languages.
  • Integrate complex systems that instantiate both the company's and third party IP.
  • Contribute to all aspects of design success from specification to production.
  • Apply our state-of-the-art IP to ASIC and FPGA products in the real world.
  • Define and improve high-quality design methods and processes.
  • Mentor and guide other ASIC design engineers.
  • Guides the successful completion of major programs and projects
  • Identifies opportunities to apply AI for continuous improvement and innovation

 

Knowledge, Skills and Abilities:

  • Solid technical background with at least 5 years of experience in FPGA or ASIC product development
  • Ability to communicate clearly in person and in written documentation
  • Degree in Computer Engineering, Computer Science, Electrical Engineering or related field
  • In-depth knowledge and experience with digital architectures and design methods such as RTL coding, synthesis, place-and-route, timing closure, constrained-random and formal verification
  • Strong analytical and problem solving skills
  • attention to detail
  • A Willingness to roll up one’s sleeves to get the job done
  • Skilled at working effectively with cross functional teams

#LI-Hybrid

Salary Note

This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled.

Combined Salary Range

USD $176,512.00 - USD $187,000.00 /Yr.

Company Overview

General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!

Equal Opportunity Employer / Individuals with Disabilities / Protected Veterans

Frequently Asked Questions

Is the salary disclosed for the Lead ASIC Digital Design Engineer position at gdms?
The salary for this Lead ASIC Digital Design Engineer role at gdms is not publicly listed. Click "Apply Now" to learn more about the compensation package on their official careers page.
Where is the Lead ASIC Digital Design Engineer position at gdms located?
This Lead ASIC Digital Design Engineer role at gdms is based in Annapolis Junction, MD, US, Bloomington, MN, US, Boise, ID, US, Salt Lake City, UT, US, Telework-Telework, US. The position is listed as on-site or hybrid. Check the full job description or apply directly to confirm the work arrangement.
Is the Lead ASIC Digital Design Engineer role at gdms full-time or part-time?
This is listed as a OTHER position. It is posted as a Lead ASIC Digital Design Engineer role in the Engineering-Hardware department at gdms.
Which team or department does the Lead ASIC Digital Design Engineer at gdms belong to?
This Lead ASIC Digital Design Engineer position is part of the Engineering-Hardware department at gdms. See the full job description for more information about the team structure and responsibilities.
How do I apply for the Lead ASIC Digital Design Engineer position at gdms?
Click the "Apply Now" button on this page. You will be redirected to gdms's official application portal hosted on icims where you can submit your application directly.
When was the Lead ASIC Digital Design Engineer job at gdms posted?
This Lead ASIC Digital Design Engineer position at gdms was posted on Mar 1, 2026. Apply as soon as possible — early applications are often reviewed first.
Lead ASIC Digital Design Engineer
gdms
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