Design Verification (DV) Engineer

latticesemi· Engineering
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🌍 Remote📍 Bayan Lepas, Penang, MYFULL TIME

About this role

Lattice Overview

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Responsibilities & Skills

Responsibilities & Skills:

We are seeking a IP DV engineer with significant hands-on experience in pre-silicon Design verification, verification methodologies and UVM/OVM.

  • Develop and Review Test Plan based on design specification
  • Develop constrained-Random verification environment for complex DUT
  • Implement coverage metrics using cover point and assertion
  • Create and debug tests for DUT
  • Resolve bugs with remote designers

Requirements:

  • Good understanding of verification process from test plan to coverage completion
  • Strong communication and Analytical skills
  • Understanding of HDL (Verilog, SystemVerilog)
  • Experience with designing with FPGA is a plus
  • Programming skills (e.g.: C/C++, Perl, TCL or Python).
  • Experience in following technology areas are an added advantage : High speed SERDES protocols (PCIe, Ethernet, CPRI or JESD204B/C, USB), Memory (DRAM, SRAM, Flash, DMA), Interconnect (AMBA AXI, AHB, APB), Peripherals (SPI, I2C or I3C)

Education and General:

  • BS/MS/PhD in Electronics or Computer Engineering minimum of 2 years of SystemVerilog/UVM
  • Independent and self-motivated, capable of executing under dynamic environment and uncertainties

Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.

Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 800 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.

Lattice

Feel the energy.

Frequently Asked Questions

Is the salary disclosed for the Design Verification (DV) Engineer position at latticesemi?
The salary for this Design Verification (DV) Engineer role at latticesemi is not publicly listed. Click "Apply Now" to learn more about the compensation package on their official careers page.
Is the Design Verification (DV) Engineer job at latticesemi remote?
Yes, this Design Verification (DV) Engineer position at latticesemi is remote, with team members based in Bayan Lepas, Penang, MY. You can work from home or anywhere in the supported regions.
Is the Design Verification (DV) Engineer role at latticesemi full-time or part-time?
This is listed as a FULL TIME position. It is posted as a Design Verification (DV) Engineer role in the Engineering department at latticesemi.
Which team or department does the Design Verification (DV) Engineer at latticesemi belong to?
This Design Verification (DV) Engineer position is part of the Engineering department at latticesemi. See the full job description for more information about the team structure and responsibilities.
How do I apply for the Design Verification (DV) Engineer position at latticesemi?
Click the "Apply Now" button on this page. You will be redirected to latticesemi's official application portal hosted on icims where you can submit your application directly.
When was the Design Verification (DV) Engineer job at latticesemi posted?
This Design Verification (DV) Engineer position at latticesemi was posted on May 12, 2026. Apply as soon as possible — early applications are often reviewed first.
Design Verification (DV) Engineer
latticesemi
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