Principal Verification Engineer

This role is based in our Bangalore, India office.

We are looking for a very experienced verification engineer who can not only strengthen the team through their technical expertise but also bring leadership and grow the verification business within EnSilica.

The role requires a good understanding of different methodologies, but particularly SystemVerilog and UVM. Faced with a new project, you will have the ability to quickly assimilate the verification challenge and help define an effective and pragmatic verification strategy and gain the support of the end-customer for the chosen approach. You understand the importance of monitoring key metrics to assess progress and predict the end-point for the verification process.

Your Key Responsibilities

• Verification specialist working on customer and internal projects – often as the verification lead.
• Provide high-class verification support to a wide range of projects using a range of advanced verification techniques including constrained random, coverage driven, assertion-based and formal methods.
• As a verification lead you would also be responsible for the development of a comprehensive verification strategy and plan, along with the architecting and development of the complete test environment.
• Active participation in the verification community to drive the introduction of new and effective techniques within our business – to help solve the verification challenges faced by our customers.
• Close working with our customers to build a strong relationship that results in repeat business.

Your Key Skills and Experience

• 1st or 2.1 Electronics, Physics or Computer Science from a Tier 1 group University.
• 10+ years’ experience in industry working on a variety of verification projects.
• Extensive knowledge of verification methodologies particularly UVM and SystemVerilog.
• Strong experience in the specification and implementation of verification infrastructures, test benches, models, assertions and functional tests in Verilog and SystemVerilog.
• Familiarity with constrained random verification methodologies, code coverage analysis and running regression tests.
• Strong VHDL/Verilog RTL.
• Very good understanding of modern verification flows and methodologies and able to influence the EnSilica one toward continuous improvement.
• Ideally you will be familiar with both Mentor Questa and Cadence Incisive tool and ideally some exposure to low power verification using UPF based flows.
• A good understanding of functional safety and quality processes, to achieve ISO26262 or similar standard’s compliances will be considered as a strong plus.

Your Personality

• Good communication and interpersonal skills, which enable you to interface easily and effectively with cross-functional stakeholders in an international environment.
• Strong and effective presentation skills, able to operate at multiple levels including senior management.

• Self-motivated achiever who gains satisfaction from providing excellent customer service and has a ‘can-do’ attitude.

• Happy to take ownership of issues and provide suitable solutions.

• You think holistically, are creative, and have a quick grasp, which enables you to maintain an overview in complex situations and make well-founded decisions.

• A team player, ideally with experience collaborating within the international, cross-functional environments.
• Adaptable and wiling to embrace change.