Senior FPGA Engineer

seakrengineering· Engineering
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About this role

Company Description

Join SEAKR Engineering, a leading-edge provider of advanced electronics for space applications. Pushing the boundaries of technology on a mission to change the world for the better from space.

Job Description

Seeking an FPGA Engineer who has extensive knowledge of digital circuit design, state machines, Boolean math and FPGAs.

Candidate shall have experience with

  • Completing multiple FPGA or ASIC design using Verilog and/or VHDL, including at least one of moderate complexity
  • Demonstrate knowledge and development of a test bench with self-checking and simulation (including back annotated timing) for given FPGA modules, top level FPGA, and system with multiple FPGAs
  • FPGA technology differences (Xilinx vs Actel/Microsemi)
  • FPGA process and development flows, especially flows using Synplify Pro, ISE, Vivado and Libero
  • Scripting languages such as TCL or Python
  • Leading small sized teams in order to develop moderately complex systems according to program schedule expectations

Required skills

  • FPGA design experience including thorough design documentation, completion and review of RTL blocks, participation in code reviews, significant RTL debug, and working knowledge of CDC, reset and clock design 
  • Ability to solve digital lab debug problems with use of lab tools such as bench supplies, scopes and logic analyzers 

Knowledge of RTL design techniques for radiation upset mitigation and experience using multiple RTL languages are a plus.

Qualifications

  • Candidate shall also have leadership skills and ability to provide support and technical direction to junior engineers.  
  • Clear written and verbal communication skills are required.
  • A Bachelor's degree in Electrical Engineering or Computer Science is desired. 
  • Must have at least 10+ years of FPGA experience.

Additional Information

Compensation: Base pay range is $130,000-185,000 depending on qualifications. SEAKR has very rich medical, dental and vision insurance plans, along with a generous 401(k) retirement plan. In addition to base salary, employees are eligible for a year-end bonus. SEAKR offers a variety of paid leave, such as vacation, sick, bereavement, and FMLA.

SEAKR is an Equal Opportunity Employer - All your information will be kept confidential according to EEO guidelines. 

US Citizenship Required

Applications will be accepted until 6/19/26

Frequently Asked Questions

Is the salary disclosed for the Senior FPGA Engineer position at seakrengineering?
The salary for this Senior FPGA Engineer role at seakrengineering is not publicly listed. Click "Apply Now" to learn more about the compensation package on their official careers page.
Where is the Senior FPGA Engineer position at seakrengineering located?
This Senior FPGA Engineer role at seakrengineering is based in CO, Englewood, Englewood, CO, United States, us. The position is listed as on-site or hybrid. Check the full job description or apply directly to confirm the work arrangement.
Is the Senior FPGA Engineer role at seakrengineering full-time or part-time?
This is listed as a Full time position. It is posted as a Senior FPGA Engineer role in the Engineering department at seakrengineering.
Which team or department does the Senior FPGA Engineer at seakrengineering belong to?
This Senior FPGA Engineer position is part of the Engineering department at seakrengineering. See the full job description for more information about the team structure and responsibilities.
How do I apply for the Senior FPGA Engineer position at seakrengineering?
Click the "Apply Now" button on this page. You will be redirected to seakrengineering's official application portal hosted on smartrecruiters where you can submit your application directly.
When was the Senior FPGA Engineer job at seakrengineering posted?
This Senior FPGA Engineer position at seakrengineering was posted on Jun 8, 2026. Apply as soon as possible — early applications are often reviewed first.
Senior FPGA Engineer
seakrengineering
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