FPGA/RTL Design Engineer – III (W2 Only)
About this role
Company Description
About Collabera
Collabera is the largest minority-owned Information Technology (IT) staffing firm in the U.S., with more than $525 million in sales revenue and a global presence that represents approximately 10,000 professionals across North America (U.S., Canada), Asia Pacific (India, Philippines, Singapore, Malaysia) and the United Kingdom. We support our clients with a strong recruitment model and a sincere commitment to their success, which is why more than 75% of our clients rank us amongst their top three staffing suppliers.
Not only are we committed to meeting and exceeding our customer’s needs, but we are committed to our employees’ satisfaction as well. We believe our employees are the cornerstone of our success and we make every effort to ensure their satisfaction throughout their tenure with Collabera. As a result of these efforts, we have been recognized by Staffing Industry Analysts (SIA) as the “Best Staffing Firm to Work For” for four consecutive years since 2012. With over forty offices globally and a presence in seven countries, Collabera provides staff augmentation, managed services and direct placement services to Global 2000 Corporations. Collabera is ranked amongst the top 10 IT staffing firms in the U.S., and for the past 24 years we have continued to grow rapidly year after year.
For consultants and employees, Collabera offers an enriching experience that promotes career growth and lifelong learning. Visit www.collabera.com to learn more about our latest job openings.
Awards and Recognitions
--Staffing Industry Analysts: Best Staffing Firm to Work For (2015, 2014, 2013, 2012)
--Staffing Industry Analysts: Largest U.S. Staffing Firms (2015, 2014, 2013)
--Staffing Industry Analysts: Largest Minority Owned IT Staffing Firm in the US.
Job Description
Position: FPGA/RTL Design Engineer – III
Location: Hillsboro, OR
Duration: 4 + Months
Job Description:
This is a senior RTL design engineer position. Primary responsibilities include:
•Working with IP designers and DFx engineers to define and scope design requirements and develop specifications for testing a given IP on a test chip
•Implementing the above mentioned spec/design in RTL
•Working with pre-silicon verification team to develop test-plans and verification collaterals
•Working with the physical design team for floor-plan and timing convergence
•Working with post-silicon validation teams to resolve silicon-level sightings
•Working with IP designers and 3rd party IP vendors to define and develop specifications for evaluating/testing inter-operability of soft IPs (eg. DDR memory controllers) with Intel Hard IP
Qualifications
You should possess a Bachelor or a Master degree in Electrical Engineering with at least 8+ years of relevant industry experience. Additional qualifications include:
•Previous design experience with ARM based SoC, including AXI/ACE and APB bus protocols
•Experience in HDL design with Verilog/SystemVerilog
•Experience with ASIC and/or SoC design flows and methodology, including CPF/UPF flows
•Experience with industry standard RTL design, simulation, and formal verification tools
•Experience in synthesis and development of timing constraints
•Scripting abilities (perl/tcl)
•Strong written/verbal communication skills are a must, as you will be working, influencing and collaborating with teams in.
Additional Information
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