Design Verification Engineer | ASIC Verification Engineer (UVM/SystemVerilog)
Erbity Private Limited
Full time
Design Verification Engineer | ASIC Verification Engineer (UVM/SystemVerilog)
Erbity Private Limited· Verification Engineering
About this role
If breaking designs before tapeout sounds fun, you’re exactly who this is for.
- 4–6 years in IP/Block/Subsystem verification
- Strong expertise in SystemVerilog and UVM methodology
- Experience building test plans, environments, and testbenches
- Strong RTL debugging, assertions, and coverage analysis
- Knowledge of AXI/AHB and protocols like DDR, PCIe, NVMe
- Experience in end-to-end verification from plan to signoff
- Exposure to mentoring and working in global teams
- Strong communication and problem-solving skills
If you believe first-pass silicon is discipline, not luck, let’s connect.
Design Verification Engineer | ASIC Verification Engineer (UVM/SystemVerilog)
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Frequently Asked Questions
Is the salary disclosed for the Design Verification Engineer | ASIC Verification Engineer (UVM/SystemVerilog) position at Erbity Private Limited?
The salary for this Design Verification Engineer | ASIC Verification Engineer (UVM/SystemVerilog) role at Erbity Private Limited is not publicly listed. Click "Apply Now" to learn more about the compensation package on their official careers page.
Where is the Design Verification Engineer | ASIC Verification Engineer (UVM/SystemVerilog) position at Erbity Private Limited located?
This Design Verification Engineer | ASIC Verification Engineer (UVM/SystemVerilog) role at Erbity Private Limited is based in Hyderabad, Telangana, India. The position is listed as on-site or hybrid. Check the full job description or apply directly to confirm the work arrangement.
Is the Design Verification Engineer | ASIC Verification Engineer (UVM/SystemVerilog) role at Erbity Private Limited full-time or part-time?
This is listed as a Full time position. It is posted as a Design Verification Engineer | ASIC Verification Engineer (UVM/SystemVerilog) role in the Verification Engineering department at Erbity Private Limited.
Which team or department does the Design Verification Engineer | ASIC Verification Engineer (UVM/SystemVerilog) at Erbity Private Limited belong to?
This Design Verification Engineer | ASIC Verification Engineer (UVM/SystemVerilog) position is part of the Verification Engineering department at Erbity Private Limited. See the full job description for more information about the team structure and responsibilities.
How do I apply for the Design Verification Engineer | ASIC Verification Engineer (UVM/SystemVerilog) position at Erbity Private Limited?
Click the "Apply Now" button on this page. You will be redirected to Erbity Private Limited's official application portal hosted on workable where you can submit your application directly.
When was the Design Verification Engineer | ASIC Verification Engineer (UVM/SystemVerilog) job at Erbity Private Limited posted?
This Design Verification Engineer | ASIC Verification Engineer (UVM/SystemVerilog) position at Erbity Private Limited was posted on Mar 31, 2026. Apply as soon as possible — early applications are often reviewed first.
Design Verification Engineer | ASIC Verification Engineer (UVM/SystemVerilog)
Erbity Private Limited
You'll be redirected to Erbity Private Limited's official application page on workable.