Principal FPGA Engineer

Welcome!

Our Growth is Creating Great Opportunities!

Our team is expanding, and we want to hire the most talented people we can.   Continued success depends on it!  Once you've had a chance to explore our current open positions, apply to the ones you feel suit you best and keep track of both your progress in the selection process, and new postings that might interest you!

Thanks for your interest in working on our team!

We are looking for a motivated Principal FPGA Engineer to join our team in Raanana.

You will have the chance to develop your own skills in a flexible and energetic work atmosphere with friendly and experienced colleagues. You will have helpful supervision, opportunity to learn, modern tools and flexible work culture.

If you want to be a part of our growing company that is driven by innovation and is focused on building a future together with our employees, consider applying. 

Principle duties and responsibilities

• Design and develop FPGA/ASIC solutions across the full product lifecycle, including feasibility studies, architecture definition, implementation, verification, and production support

• Work independently to deliver high-quality engineering solutions with minimal supervision.

• Operate at the system architecture level across multiple design domains.

• Serve as a Subject Matter Expert (SME) in one or more technical areas and provide consulting to other teams.

• Lead and contribute to complex, high-impact projects critical to the business.

• Integrate AI tools in FPGA/ASIC development process.

• Mentor and provide technical guidance to junior and senior engineers.

• Collaborate with engineering management and product teams on:

  • Development planning

  • Architecture decisions

  • Resource estimation

  • Project scheduling

• Drive improvements in design, verification, and backend methodologies.

• Participate in design, specification, and test reviews at IP/module/system level.

• Ensure FPGA/ASIC design requirements are met on schedule.

• Represent the company in technical forums, customer meetings, or industry standards committees.

Supplementary Tasks:

• Demonstrated ability to complete the full product design life cycle on a portion of the system involving multiple components.

• Designs, modifies, and develops, writes and implements software, hardware, firmware or control plane programming applications /operating systems.

• Virtualization - Development and testing for ADVA Hybrid virtualization products.

• Capable of working independently on the assigned design activities with minimal supervision.

• Comprehensive understanding of the product architecture, design, processes, tools, etc. required to perform their assigned design activities.

Qualifications, Skills

• Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or related field.

• 10+ years of relevant experience (8+ with MSc).

• Experience in at least 5 full product design cycles (telecom/datacom preferred).

• Proven experience with large-scale FPGA or ASIC design and/or verification.

• Technical Skills

• Strong expertise in HDL languages: Verilog, VHDL, SystemVerilog

• Experience with scripting (Shell, Tcl) for automation and analysis

• Solid knowledge of:

  • High-speed digital design

  • PLLs, clocking, and reset architectures

  • Physical implementation of high-speed systems

• Experience building scalable simulation and verification environments.

• Ability to integrate and validate third-party IPs.

• Experience with AI tools to improve workflow.

• Strong Linux/Unix and Windows environment experience.

Success Criteria:

• Recognized technical expert within the team or organization.

• Provides mentorship and technical leadership.

• Influences architecture decisions and product roadmap.

• Drives best practices across design and verification processes.

Benefits

• Possibility to work in an international, multicultural environment.

• Strong team-oriented and friendly work culture

• Spot Awards. 

• CSR program - Employee volunteerism and community involvement.