Analog Layout Design Engineer
altera
Full time
Front End ASIC RTL/Logic Senior Design Engineer
altera· 754 Altera Semiconductor Technology (M) Sdn. Bhd.
About this role
Job Details:
Job Description:
Responsible to lead, define & implement the design (micro-architecture, RTL, linting, CDC, SDC, UPF/power gating, synthesis) of high speed digital design in next generation IO in cutting edge technology node with multi GigaHz design.
Work closely with verification team for design test plan and validation review and back-end team for floor planning, physical implementation, STA timing closure.
Work on post Silicon debug/characterization support of the designs.
Qualifications:
BS/MS or PhD in Electronics Engineering with minimum of 10 years of ASIC frontend experience
Strong in communication, leadership, investigation, problem solving & analytical skill
Proficiency with RTL coding using HDL language(s). Familiarity with logic simulation and debug environments
Knowledge of Spyglass, Synthesis, STA (PT), UPF, UVM, Spice and DFT.
Knowledge scripting desirable
Job Type:
RegularShift:
Shift 1 (Malaysia)Primary Location:
Penang 15, Penang, MalaysiaAdditional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Frequently Asked Questions
Is the salary disclosed for the Front End ASIC RTL/Logic Senior Design Engineer position at altera?
The salary for this Front End ASIC RTL/Logic Senior Design Engineer role at altera is not publicly listed. Click "Apply Now" to learn more about the compensation package on their official careers page.
Where is the Front End ASIC RTL/Logic Senior Design Engineer position at altera located?
This Front End ASIC RTL/Logic Senior Design Engineer role at altera is based in Penang 15, Penang, Malaysia. The position is listed as on-site or hybrid. Check the full job description or apply directly to confirm the work arrangement.
Is the Front End ASIC RTL/Logic Senior Design Engineer role at altera full-time or part-time?
This is listed as a Full time position. It is posted as a Front End ASIC RTL/Logic Senior Design Engineer role in the 754 Altera Semiconductor Technology (M) Sdn. Bhd. department at altera.
Which team or department does the Front End ASIC RTL/Logic Senior Design Engineer at altera belong to?
This Front End ASIC RTL/Logic Senior Design Engineer position is part of the 754 Altera Semiconductor Technology (M) Sdn. Bhd. department at altera. See the full job description for more information about the team structure and responsibilities.
How do I apply for the Front End ASIC RTL/Logic Senior Design Engineer position at altera?
Click the "Apply Now" button on this page. You will be redirected to altera's official application portal hosted on workday where you can submit your application directly.
Front End ASIC RTL/Logic Senior Design Engineer
altera
You'll be redirected to altera's official application page on Workday.