Staff Design Verification Engineer (AI/ML)

About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.

About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds. ADI designs and manufactures analog, mixed-signal, and digital signal processing technologies that solve the toughest engineering challenges across industrial, automotive, communications, healthcare, and consumer markets. With approximately 24,000 employees worldwide and revenue exceeding $11 billion in FY25, ADI combines deep engineering expertise with customer collaboration to deliver innovation at the Intelligent Edge.

About the Role

As a Staff Design Verification Engineer in ADI's Shanghai design center, you will develop and execute verification strategies for complex analog and mixed-signal ICs, from test planning through coverage closure. You will apply AI/ML techniques to improve regression efficiency, debug throughput, and coverage analysis. Your work will contribute to product quality and delivery across multiple business units, ensuring ADI's next-generation mixed-signal and power management products meet rigorous quality standards.  This role involves close collaboration with global design teams across multiple time zones to support semiconductor process development alongside the teams building ADI's next-generation technologies.

Key Responsibilities

• Apply AI/ML methodologies for failure clustering, regression triage, anomaly detection, and coverage optimization
• Develop and execute verification plans, defining coverage models and success metrics for mixed-signal IC blocks and subsystems
• Build and maintain SystemVerilog/UVM testbenches, monitors, scoreboards, and automated checkers for mixed-signal verification
• Perform functional coverage analysis and drive coverage closure toward tape-out readiness
• Support silicon correlation by comparing simulation expectations against lab measurements and refining tests based on results
• Participate in verification reviews, contributing technical analysis on coverage completeness and methodology improvements
• Collaborate with design, applications, and test teams to ensure verification reflects real use-cases and operating conditions

Required Skills and Experience

• MSEE or MSCE with 7+ years of IC verification experience, or PhD with 5+ years (BSEE/BSCE with equivalent depth considered)
• Strong proficiency in SystemVerilog and UVM with experience building coverage-driven verification environments for mixed-signal products
• Demonstrated ability to deliver verification through tape-out sign-off and production release
• Solid Python scripting skills with experience applying AI/ML techniques to enhance verification productivity
• Knowledge of formal verification, assertion-based methodology, and clock domain crossing analysis
• Proficiency with Cadence verification tools: Xcelium (simulation), JasperGold (formal verification)
• Fluent in Mandarin; strong English written and verbal communication skills for cross-site collaboration
• Ability to collaborate effectively across global, cross-functional teams

Preferred Qualifications

• Curiosity and initiative to explore AI/ML techniques and emerging tools that can transform verification workflows, with an enthusiasm for discovering more effective ways of working
• Experience with mixed-signal and AMS verification techniques including Verilog-AMS, real-number modeling, and behavioral abstraction
• Experience with gate-level simulation, SDF back-annotation, and post-layout verification
• Strong analytical and problem-solving abilities
• Ability to work effectively in a collaborative team environment

Technical Scope

• Application of AI/ML-driven workflows for regression analytics, failure classification, and debug acceleration
• Block-level and subsystem-level verification ownership from specification analysis through coverage closure
• Mixed-signal verification environment development including analog behavioral modeling and digital-analog interface checking
• Test plan authoring, coverage model implementation, and regression management

Collaboration and Impact

• Share AI/ML-driven improvements to verification workflows and best practices with team members
• Work with design, applications, and test teams to translate product requirements into verification coverage that reflects real operating conditions
• Contribute to verification reviews and cross-team technical discussions

Why Join ADI

At Analog Devices, you will work on meaningful engineering problems with real-world impact alongside world-class engineers. ADI fosters a culture of technical excellence, continuous learning, and collaboration, providing opportunities to grow while contributing to technologies that shape the future of the intelligent edge.

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.